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MRF49XA
FIGURE 3-16:
TX REGISTER USAGE
Enabling the transmitter preloads the TX latch with
0xAAAA
Do not switch the TXCEN off here, because the TX
Byte 1 is not transmitted out, it is only stored in the
internal register
SPI
Commands
(CS, SCK, SDI)
GENCREG
TXDEN = 1
PMCREG
TXCEN = 1
TX Latc h
TX Byte 1
T X Latc h
Dummy
TX Byte
PMCREG
TXCEN = 0
GENCREG
TXDEN = 0
TXCEN
Enable
Synthesizer/PA
Synt.
T tx_xtal_on (1)
PA
TX Data
0xAA
0xAA
TX Byte1
Fraction of the dummy byte
IRO
SDO (2)
Note 1: Ttx_xtal_on is the start-up time of PLL + PA with a running crystal oscillator.
2: SDO is a tri-state of CS.
FIGURE 3-17:
CS
SCK
MULTIPLE BYTE WRITE WITH TRANSMIT REGISTER
SDI
TX BYTE 1
TX BYTE 2
TX BYTE n
Transmit Register Write
SDO
(Register interrupt in TX mode*)
* The device is in Transmit (TX) mode when the RXCEN bit is cleared using the PMCREG.
? 2009-2011 Microchip Technology Inc.
Preliminary
DS70590C-page 69
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